With shrinking dimensions of various integrated circuit components, transistors such as field-effect transistors (FETs) have experienced dramatic improvement in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Nevertheless, performance improvement brought up by this type of “classic” scaling, in device dimensions, has recently met obstacles and in some cases even been challenged, when the scaling goes beyond a certain point, by the increase in leakage current and variability that are inevitably associated with the continued reduction in device dimensions. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) are particularly well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, with a thickness of about 30 nm to 100 nm, are generally required for acceptable performance in short channel devices. Silicon-on-insulator (SOI) technology allows the formation of high-speed, shallow-junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.
In an SOI substrate, a buried oxide (BOX) film made of silicon oxide is formed on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods of fabricating such SOI substrates are known, one of which is Separation-by-Implanted Oxygen (SIMOX), wherein oxygen is ion implanted into a single crystal silicon substrate to form a BOX film. Another method of forming an SOI substrate is wafer bonding, wherein two semiconductor substrates with silicon oxide surface layers are bonded together at the silicon oxide surfaces to form a BOX layer between the two semiconductor substrates.
Shallow junction transistors use shallow trench isolation (STI) techniques to separate devices and circuits. STI techniques significantly increase the manufacturing cost because the STI process requires a large number of processing steps and apparatus, such as thermal oxidation, silicon nitride chemical vapor deposition (CVD), silicon nitride wet etch, reactive ion etch (RIE), high density plasma (HDP) silicon oxide deposition, wet clean, chemical-mechanical polishing (CMP), and photolithography. Uniformity and yield of wafers is also a concern in view of the additional processing steps necessitated for STI processing.
Scaling CMOS devices has pushed the number of parameters out of a negligible region to the point of becoming a significant circuit design factors. One of the important device parameters is the short-channel control and Extremely thin Silicon-On-Insulator (ETSOI), both becoming a new class of transistors designed for this propose. ETSOI, a fully depleted charge carriers transistor device, (i.e., having a concentration of charge carriers present at 300K in the channel in the order of 103 atoms/cm3 or less), uses an ultra-thin silicon channel wherein the majority carriers are fully depleted (FD) during operation. The challenge of this class of transistors is its Vt variation and high extrinsic resistance (Rext).
The FDSOI transistor threshold voltage Vt varies as a function of the first power order of the channel dopant, which is also due to the atomical channel silicon thickness variation rather than the 0.4 order for a conventional PDSOI device. This is because of the compensation factor in a partially depleted (PD) FET, which captures the change of the depletion depth with the doping, and which does not exist in a fully depleted device. As a result, Vt varies more strongly with the doping variation, such as random doping fluctuations.
Moreover, an entirely new factor, i.e., the body thickness variation, is introduced. Since the ETSOI devices are fully depleted, changes in body thickness result in changes in the charge in the body which, by Gauss' law, results in changes in the channel potential, altering the threshold voltage.
Many advanced transistor structures aiming at reducing short-channel effects (SCE) includes drain induced bias lowering (DIBL) and sub-threshold swing. As the transistor become smaller, SCE has shown to be the dominant factor. Accordingly, structures such as UTSOI, ETSOI Backgate and Double gate, employ a very thin silicon channel which is fully depleted of majority carriers during operation, providing a superior control on the SCE. Backgate device holds the promise of the relief of random doping fluctuations since Vt can be set by the backgate potential, reducing the dependence of channel doping.
As transistors shrink further in dimension, the ability to scale down the gate length of conventional bulk silicon MOSFET diminishes due to SCE. Single Gate Fully Depleted Semiconductor-on-Insulator (FDSOI) technology has been established as one solution to reduce SCE as well as to reduce unwanted parasitic capacitances.
However, the Single Gate FDSOI technology may require a stringent thickness requirement and uniformity control of the thin silicon film on insulator to achieve full depletion. Additionally, the aforementioned Drain-Induced Virtual Substrate Biasing (DIVSB) effect is another challenge for Single Gate FDSOI technology. In contrast, Double-Gate FDSOI technology may necessitate a less stringent requirement on the thickness of a semiconductor on insulator, may reduce the Drain Induced Virtual Substrate Biasing (DIVSB) effect, and may maintain better SCE control and high trans-conductance.
For illustrative purposes, and with reference to FIG. 1, a prior art extremely-thin SOI device is shown that includes a buried oxide layer 110 on a substrate 100, an ETSOI layer 120 on the buried oxide layer, and a gate stack on the ETSOI layer. The gate stack includes a high-k oxide layer 131 upon the ETSOI layer, followed by a high-k metal gate (MGHK) 132 superimposed on top of the high-k oxide layer. A metal region 133 is positioned above the MGHK layer. Each of the raised source/drain regions (RSD) 130 is placed on the ETSOI layer, abutting at spacers 150.
In a first aspect, an embodiment of the invention describes a novel backgate tungsten with the raised source/drain regions (RSD) 130 is placed on the ETSOI layer, abutting at spacers 150.
Conventional ETSOI device provided with a thick buried oxide Box 105 have experimentally demonstrated that Short Channel Effect (SCE) can only improve by approximately 20 to 40%. As further scaling of HKMG gate stack dimension, a better SCE control is needed.
The thickness of ETSOI layer 105 ranges from 6 nm to 20 nm. Due to the extremely thin SOI layer 105, the active SD and Extension regions experience create difficulties for dopant implants and activation annealing. Although implants can be conducted, only partial dopants are activated due to lack of silicon re-crystallization. The sheet resistance from both active regions is so elevated that its electrostatic performance is severely degraded. Employing a raised source/drain (RSD) 130 can be used to levitate this issue partially, but it is the Extension resistance that remains the dominant factor for performance degradation. In-situ doping RSD is another technique used for ETSOI devices and high RTA (rapid thermal annealing) temperature is incorporated therein to reduce the resistivity and drive dopants under HKMG stack. Because halo implant for a good Vt control is not applicable, resulting in a high Vt and device punch-through.
In view of the aforementioned considerations, there is a need for ETSOI devices having a separate backgate enabling on-demand Vt adjustments that is not available in single gate or tied-double gate devices in order to improve the control of Vt variations due to channel dopants and silicon body thickness.